In typical microprocessors, the main storage is provided with a total translation table that identifies the correspondence between virtual addresses and physical addresses within the main storage (memory). In such a conventional microprocessor, however, a long processing time is required each time the translation table in the main storage is accessed to perform an address translation. Because a slow address translation reduces the processing speed, an address translation device such as the one shown in FIG. 6 has conventionally been provided.
In the FIG. 6 address translation device, a TLB (translation lookaside buffer) circuit 1 outputs a physical page number 3 in response to a virtual page number 2 provided to the TLB circuit 1 by the processor. TLB circuit 1 includes a correspondence table between the virtual addresses and the physical addresses, so that the physical address can be obtained from the virtual address on the basis of a table look-up operation. Most systems perform address translation by use of a TLB circuit. When address translation is not executed within a circuit such as the TLB circuit 1, the address translation table provided for the main storage is eventually accessed.
Since processing speed is lowered markedly when the address translation table of the main storage is accessed, attempts have been made to increase the probability that the address translation can be executed by the TLB circuit 1. In other words, attempts have been made to increase the hit ratio for the TLB circuit 1. For this purpose a four-way set associative type or a full associative type have been adopted as TLB circuits.
FIG. 7 is a block diagram showing a conventional address translation device of the four-way set associative type. In FIG. 7, a memory array 12 is provided with four virtual page address holding memories 10a, 10b, 10c and 10d and with four physical page address holding memories 11a, 11b, 11c and 11d. Individual ones of the virtual page address memories are interleaved with corresponding ones of the physical page address memories. When a virtual page number 2 is provided to the address translation device, the virtual page number 2 is compared with the contents of the four virtual page address holding memories 10a, 10b, 10c and 10d, respectively. If the virtual page number 2 matches the contents of one of these virtual page address holding memories 10a, 10b, 10c and 10d, the comparators 13a, 13b, 13c and 13d output a corresponding signal 14a, 14b, 14c or 14d, respectively. On the basis of the match signals 14a, 14b, 14c and 14d, a selected one of the four tri-state (three-state) buffers 15a, 15b, 15c and 15d outputs the contents of one of the four physical page address holding memories 11a, 11b, 11c and 11d, respectively as a physical page number 3.
In the conventional address translation device described above, the virtual page address 2 is compared to four addresses in parallel, allowing the hit ratio to be improved so that the processing speed is increased to the extent that the main storage is not accessed. In the conventional address translation device, on the other hand, there exists a problem of increased power consumption. In the case of the full associative type of address translation device, since the number of address comparisons executed corresponds to the number of entries in the comparison table, there exists a serious problem of increasing power consumption with increasing numbers of comparisons. Thus, if the number of corresponding address pairs within a memory array 12 is increased to increase the hit ratio, the power consumption inevitably increases due to the increased number of compare operations required to identify a hit.